The invention relates in general to the field of digital television, and in particular to a circuit for displaying graphics data along with video data in a digital television receiver.
Highly-integrated chip sets including a digital TV decoder are available for digital television sets. The digital TV decoder typically has an MPEG video decoder, a unit for outputting decoded video data, and an on screen display (OSD) unit. The OSD unit has the function, for example, of displaying settings for the television set such as volume, color, contrast, brightness, etc. on the screen, but may be used to display any type of information such as data from the Internet. The OSD unit retrieves the graphics data in the same synchronization raster and pixel raster as the video data from a memory, which stores both video data and graphics data, and displays the graphics data on the television screen.
If, on the other hand, an application requires independent output of graphics and video data, complex circuits typically must be provided since, for example, in a 100 Hz television receiver, graphics data do not pass through an algorithm for raising the refresh rate to 100 Hz, as this would be superfluous. Problems may also occur in applications, for example, in which decoded digital video data for recording are fed to an analog video recorder in the background. In this case, the video and/or graphics data are displayed by the television receiver, while the analog video recorder records the video data. Currently, no integrated chip set is available for such applications.
What is needed is a system for displaying graphics in a digital television receiver which avoids the above problems.